1. Technical Field
The present invention relates generally to semiconductor devices and in particular to electrical programming of on-chip fuses of semi-conductor devices. Still more particularly the present invention relates to reducing fusing time during electrical programming of on-chip fuses of semiconductor devices.
2. Description of the Related Art
Current semiconductors and other similar devices are often manufactured with a large number of fuse elements which are used to invoke the replacement of failing cells or components, and provide DAC trimming, etc. During testing of the device, selected fuses are usually blown by either a laser beam or an electrical current, depending on the design of the fuse/device. In an electrical fuse design, electronically programmable fuses are blown by passing a current through the fuse link. The electrical current then causes a permanent change to the resistance of the fuse. The fuses that are blown are selected via one or more programming methods, which are generally known to those skilled in the art.
FIG. 1 illustrates a prior art schematic of a portion of a device with fuse elements (eFuse circuits) and input signals/logic. Only two fuses are illustrated, although a complete device may comprise a much larger number of fuses. As shown, the electrical fuse circuits are fabricated with two latches per fuse. The first latch, which is called the fuse sense latch (or fuse latch) 103 is utilized to read the state of the fuse and is also utilized during the fusing process to enable/disable the blowing of the associated fuse. The second latch, called the pattern latch 113, is utilized to store the redundancy solution that was calculated for the device. According to FIG. 1, the fuse latch 103 is in the “upper” register and the pattern latch 113 is in the “lower” register.
As illustrated, the two chains of latches (fuse latches 103 and pattern latches 113) are connected in serial fashion, with each latch receiving it's shift input from the previous latch and sending it's shift output to the next latch in the chain. With this topology, enabling an electrical fuse to be programmed requires that both the output of the fuse latch 103 and pattern latch 113 corresponding to a specific fuse be set high (utilizing and AND logic function 105). Prior to fuse programming, the FSOURCE input 109 is set to a voltage high enough to program the fuses. Other inputs, including clock inputs ACLK 110 and BCLK 111, for example, along with input logic 116–119 are utilized to set the values within the latches. During the time that both latches are set high and global input GATEN is high, the programming transistor 107 for the eFuse turns on, blowing the connected fuse 106.
A major cost adder to the production of semiconductor devices (such as ASIC—application-specific integrated circuit—logic chips) is the time and financial costs incurred when testing the device. A major portion of the testing and associated costs involves the fusing process (i.e., the process by which the fuses are selected and electrically blown). Current electrical fusing times are on the order of 200 μs per fuse. Due to the fusing current and on chip routing of relatively high voltage and high current busses, fusing multiple fuses at a time is not a practical solution for typical semiconductor devices. With fusing current as high as 15 mA per fuse, multiple simultaneous fuse blow becomes difficult and requires more device I/O's to be dedicated to the fuse blow input (called FSOURCE) supply. Using many input pads on a chip/package to support electrical fusing is not a cost effective solution. Thus, fuses are currently blown in a serial manner (i.e., one at a time) during testing because of the high fusing current and other factors describe. With electrical fuses it is desirable to reduce fusing time as much as possible.
The fusing process can require a significant amount of time compared to the overall testing time. This is mainly due to the microsecond time scale used in fusing versus the nanosecond timings used for test. The fusing time is controlled by the rate at which a single ‘1’ is clocked or shifted through the fuse latches 103. Only one fuse latch 103 is set high at a time, guaranteeing only one fuse 106 is “blown” at a time. With this design, fusing time required for one fuse is spent on every latch in the fuse latch shift chain.
For example, assume the fusing process takes 1 clock cycle to blow each fuse. Then, the number of total clock cycles required for completing the test when the fuses are serially blown equals at least the number of fuses in the device. With the large number of fuses in current devices, typically hundreds or thousands, this serial implementation requires significant time commitment and is extremely inefficient for devices that only require a small percentage of the available fuses to be blown.
Another primary concern with current designs is the area overhead incurred due to the need to individually address electrical fuses on-chip. U.S. Pat. No. 6,426,911 provides one solution that addresses this area overhead problem by creating a shift register by a serial in/serial out wiring of the fuse latches and the connection of the gates of the blow transistors to the serial out port of each fuse latch. However, the problem of fuse time remains as the technique provided by the patent fails to reduce the one-by-one propagation of the signal through each latch of the fuse scan chain. That is, the programming information is propagated from latch to latch as a single “1” acting as a pointer that activates only one fuse latch per clock cycle. Also, only one fuse is blown per clock cycle to prevent the problems associated with high electrical current and other overhead issues described above.
From the perspective of a scan path, particular types of latches are provided to enable a scan chain evaluation for the device. In FIG. 1, the fuse scan chain connections are illustrated with LSSD (level sensitive scan design) latches. The fuse latches 103 and pattern latches 113 are serially connected and wired into the fuse logic. The fuse pattern is loaded into the lower or pattern register prior to programming. The upper or fuse register has a single bit (“1”) loaded and “walked” down the shift register. The clock frequency utilized to clock the fuse register gives simple control over the fuse programming time.
As illustrated by FIG. 1, each serial register of latches (LSSD scan latches) comprises a dual latch. The first latch in an LSSD scan latch is called the L1 and is loaded with clock signal ACLK 110. The second latch in the LSSD scan latch is called the L2 and is loaded with signal BCLK 111. When the fuse 107 is sensed, the value is sensed into the latch L1. Sensing of the fuse is done with a single ended resistor divider technique that is generally known to those skilled in the art. If the fuse 107 is intact, the latch will be pulled low by the connection from the fuse to FSOURCE 109, which must be at 0 Volts (GND) during sensing of the fuse. If the fuse 107 is programmed (blown), the latch L1 will remain high. Once the signal that enables fuse sense goes low, the fuse latch sensing is complete.
The present invention recognizes the inefficiencies that exist in the design and testing of current devices and recognizes that it would be desirable to reduce the time and costs associated with the fusing process, particularly when only a small fraction of the total number of fuses are actually being blown. A method and device that enables efficient completion of the fuse blowing stage of device testing would be a welcomed improvement. It would be further desirable if the method and device also enabled reduced area overhead along with the reduced fusing time. These and other benefits are provided by the invention described below.